This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2000-251853, filed Aug. 23, 2000, the entire contents of which are incorporated herein by reference.
This invention relates to a semiconductor memory device using a ferroelectric film. More particularly, this invention relates to a series-connected TC parallel-unit type ferroelectric RAM (Random Access Memory) composed of a series connection of a plurality of unit cells, each unit cell being such that a ferroelectric capacitor (C) is connected between the source and drain of a cell transistor (T).
It is common knowledge that ferroelectric memories are nonvolatile, like flash memories, and have the ability to effect high-speed access and high-speed rewriting, like DRAMs. Furthermore, the ferroelectric memory is capable of operating on a lower voltage and consuming less power than the flash memory. That is, although being a nonvolatile device, the ferroelectric memory has the advantages of achieving a larger number of rewrites and a shorter write time and being capable of operating on a lower voltage and consuming less power.
The cell structure of the ferroelectric memory has been generally developed using a one-transistor one-capacitor cell.
In a conventional ferroelectric memory of FIG. 9, a plurality of memory cells MCs are placed at the intersections of word lines WLs and pair of bit lines (bit line pairs) BLs, BBLs complementary to each other, the word lines crossing at right angles with the bit line pairs, in such a manner that they are located at every other intersection. A plate electrode wire PL is placed in parallel with each of the word lines WL. Each of the plate electrode wires PLs and each of the word lines WLs are controlled by a row decoder/plate electrode wire driving circuit (RD and PD) 105 controlled according to row addresses.
Each of the bit line pairs BLs, BBLs is controlled by a sense amplifier SA controlled according to row addresses. That is, each sense amplifier SA amplifies the data read onto a pair of bit lines BL, BBL.
The read or write data is inputted or outputted via a pair of data lines (data line pair) DQ, BDQ complementary to each other.
The row decoder/plate electrode wire driving circuit 105 is controlled by a row control circuit 109.
The row decoder circuit 109 is controlled on the basis of a chip enable signal CEB transmitted over a chip enable signal wire 110 and a row address signal Adr transmitted over a row address signal wire 120.
A column decoder (CD) 115 is controlled on the basis of the output of a column control circuit 114. The column control circuit 114 is controlled on the basis of the chip enable signal CEB and a column address signal Adc transmitted over a column address signal wire 121.
A read/write control circuit 119 is controlled by the chip enable signal CEB and a read/write signal RW transmitted over read/write signal wires 111. A read data latch 113 and a write data latch 116 are controlled by the read/write control circuit 119. The read data latch 113 and write data latch 116 are connected to the pair of data lines DQ, BDQ, respectively. The read data latch 113 outputs an output signal (read data) Dout. An input signal (write data) Din is inputted to the write data latch 116.
FIG. 10 shows, in further detail, the circuit configuration of the part indicated by A or FIG. 9.
In FIG. 10, for example, four memory cells MCs are placed between bit lines BL0, BBL0 making a pair. Specifically, the gate of a first cell transistor M0 is connected to word line WL0. One electrode of a first cell capacitor C0 is connected to plate electrode wire PL0 and the other electrode of the first cell capacitor C0 is connected to one of the source and drain of the first cell transistor M0. The other of the source and drain of the first cell transistor M0 is connected to bit line BL0.
The gate of a second cell transistor M1 is connected to word line WL1. One of the source and drain of the second cell transistor M1 is connected to bit line BL0. One electrode of a second cell capacitor C1 is connected to plate electrode wire PL1 and the other electrode of the second cell capacitor C1 is connected to the other of the source and drain of the second cell transistor M1.
The gate of a third cell transistor M2 is connected to word line WL2. One electrode of a third cell capacitor C2 is connected to plate electrode wire PL2 and the other electrode of the third cell capacitor C2 is connected to one of the source and drain of the third cell transistor M2. The other of the source and drain of the third cell transistor M2 is connected to bit line BBL0.
The gate of a fourth cell transistor M3 is connected to word line WL3. One of the source and drain of the fourth cell transistor M3 is connected to bit line BBL0. One electrode of a fourth cell capacitor C3 is connected to plate electrode wire PL3 and the other electrode of the fourth cell capacitor C3 is connected to the other of the source and drain of the fourth cell transistor M3.
With this configuration, the plate electrode wires PL0, PL1, PL2, PL3 are provided for the cell capacitors C0, C1, C2, C3, respectively. The plate electrode wires PL0, PL1, PL2, PL3 are provided in the longitudinal direction of the word lines WL0, WL1, WL2, WL3, respectively.
In this connection, a ferroelectric memory with one-transistor one-capacity cells where the plate electrode wires are provided in the longitudinal direction of bit lines has been disclosed in U.S. Pat. No. 5,400,275 (Jpn. Pat. Appln. KOKAI Publication No. 4-42498). In the ferroelectric memory, for example, four memory cells MCs, as shown in FIG. 11, are placed between bit lines BL0, BBL0 making a pair.
Specifically, the gate of a first cell transistor M0 is connected to word line WL0. One electrode of a first cell capacitor C0 is connected to plate electrode wire PL0 and the other electrode of the first cell capacitor C0 is connected to one of the source and drain of a first cell transistor M0. The other of the source and drain of the first cell transistor M0 is connected to bit line BL0.
The gate of a second cell transistor M1 is connected to word line WL1. One of the source and drain of the second cell transistor M1 is connected to bit line BL0. One electrode of a second cell capacitor C1 is connected to plate electrode wire PL0 and the other electrode of the second cell capacitor C1 is connected to the other of the source and drain of the second cell transistor M1.
The gate of a third cell transistor M2 is connected to word line WL2. One electrode of a third cell capacitor C2 is connected to plate electrode wire PL0 and the other electrode of the third cell capacitor C2 is connected to one of the source and drain of a third cell transistor M2. The other of the source and drain of the third cell transistor M2 is connected to bit line BBL0.
The gate of a fourth cell transistor M3 is connected to word line WL3. One of the source and drain of the fourth cell transistor M3 is connected to bit line BBL0. One electrode of a fourth cell capacitor C3 is connected to plate electrode wire PL0 and the other electrode of the fourth cell capacitor C3 is connected to the other of the source and drain of the fourth cell transistor M3.
In this configuration, a single plate electrode wire PL0 is provided in-parallel with and between bit lines BL0, BBL0 making a pair.
With this configuration, data is read from or written into only the memory cell MC at the intersections of the word lines WL0, WL1, WL2, WL3 set at the high level and plate electrode wire PL0 driven to the high level. In this way, by reducing the number of accessed cells, the operating current can be decreased.
Although such a configuration reduces the frequency of access to the memory cells MC and the current drawn, a new problem is expected to arise: read disturb will take place. Read disturb is a phenomenon in which a cell transistor decreases the data accumulated in a memory cell (half-selected) MC which is off and eventually destroys the data.
Hereinafter, referring to FIGS. 11 and 12, read disturb will be explained.
Using a hysteresis curve in FIG. 12, the read operation of a ferroelectric memory will be explained. For example, when no voltage is applied to a PZT (lead zirconate titanate (PbZrTiO3)) film, known as a ferroelectric film, it is in the polarized state (remanent polarization) of either an upward direction or a downward direction denoted by xe2x80x9c0xe2x80x9d or xe2x80x9c1xe2x80x9d in the figure and makes a nonvolatile memory.
When a voltage is applied to the polarized PZT film, if it is in the xe2x80x9c1xe2x80x9d s state, the polarization is not reversed. If it is in the xe2x80x9c0xe2x80x9d state, the polarization is reversed. In these two cases, the amount of charge required to apply the same voltage (that is, when the same voltage is applied to one of the PZT film, the amount of charge generated at the other end of the PZT film) in the xe2x80x9c0xe2x80x9d state differs from that in the xe2x80x9c1xe2x80x9d state. By sensing the voltage difference, the data is read in the ferroelectric memory.
It is assumed that, in FIG. 11, plate electrode wire PL0 is driven with word line WL0 at the high level and word line WL1 at the low level. In addition, it is assumed that cell capacitor C1 connected to word line WL1 is in the xe2x80x9c1xe2x80x9d state, that is, in the downward polarized state. Then, even if plate electrode wire PL0 is driven, cell transistor M1 remains off because word line WL1 is closed. Consequently, no voltage difference appears at both ends of cell capacitor C1.
When the state is continued for a length of time, however, the potential at the node on the cell transistor M1 side drops because of a junction leak. Then, a potential difference appears at both ends of cell capacitor C1, which decrease the data accumulated in the cell MC and eventually destroys the data.
The following is an explanation of a ferroelectric memory capable of improving high-speed operation and high integration. For instance, U.S. Pat. No. 5,903,492 (Jpn. Pat. Appln. KOKAI Publication No. 10-255483) has disclosed a ferroelectric memory (series-connected TC parallel-unit type ferroelectric RAM) composed of a series connection of a plurality of unit cells, each unit cell being such that both electrodes of a cell capacitor (C) are connected to the source and drain of a cell transistor (T), respectively.
For example, in the series-connected TC parallel-unit type ferroelectric RAM, a plurality of memory cell blocks 132 share a pair of plate electrode wires PL, BPL (plate electrode wire pair) complementary to each other provided along the word lines WLn (n=0, 1, 2, . . . , 7) and a driving circuit 131 for driving the plate electrode wire pair of PL, BPL as shown in FIG. 13. With this configuration, the number of plate electrode wire pairs of PL, BPL and driving circuits 131 is decreased, thereby realizing a reduction in the chip size.
In the configuration of FIG. 13, each memory cell block 132 is composed of a series connection of a plurality of memory cells MCn (n=0, 1, 2, . . . , 7), each made up of a cell transistor Tn (n=0, 1, 2, . . . , 7) and a cell capacitor Cn (n=0, 1, 2, . . . , 7). The gate of each cell transistor Tn in the memory cell block 132 is connected to the corresponding word line WLn.
One end of each memory cell block 132 is connected to the corresponding plate electrode wire pair of PL, BPL. The other end of each memory cell block 132 is connected to one of the source and drain of the corresponding block select transistor 133. The gate of the block select transistor 133 is connected to any one of the block select lines BS0, BS1 forming a pair complementary to each other (block select line pair). The other of the source and drain of each block select transistor 133 is connected to the corresponding bit line pair of BL, BBL. A sense amplifier (SA) 135 is connected to the bit line pair of BL, BBL.
The plate electrode wire pair of PL, BPL is driven by a plate electrode wire driving circuit 131. Each plate electrode wire driving circuit 131 drives a plurality of memory cell blocks 132 connected to the same plate electrode wire pair of PL, BPL.
Although only two plate electrode wire driving circuits 131 are shown in FIG. 13, there are as many plate electrode wire driving circuits 131 as there are memory cell blocks 132 placed in the longitudinal direction of the bit line pair of BL, BBL. Each plate electrode wire driving circuit 131 is designed to supply different plate electrode wire driving signals to each of the plate electrode wire PL, BPL making a pair.
The word line (selected word line) WLn connected to the gate of the cell transistor Tn of the selected memory cell (selected cell) MCn goes to the low level. The remaining word lines (unselected word lines) WLn go to the high level. In this way, only the cell transistor Tn of the selected cell MCn turns off, applying a potential to both ends of the cell capacitor Cn connected in parallel with the cell transistor Tn.
The block select line pair of BS0, BS1 connected to the gate of the block select transistor 133 connected to the memory cell block 132 including the selected cell MCn goes to the high level. As a result, the memory cell block 132 is connected to the bit line pairs of BL, BBL.
Furthermore, the plate electrode wires PL, BPL connected to the memory cell block 132 including the selected cell MCn go to the high level. Then, the data is read or written from or into the memory cell MCn selected between the plate electrode wire pair of PL, BPL and the bit line pair of BL, BBL.
In contrast, the cell transistor Tn of the unselected cell MC turns off. In this case, the same potential is applied to both ends of the cell capacitor Cn of the unselected cell MC. This prevents the data from being read or written from or into the unselected cell MCn.
The above-described conventional series-connected TC parallel-unit type ferroelectric RAM has the following problem.
Although the ferroelectric RAM of FIG. 13 is capable of improving high-speed operation and high integration, it has basically the same number of cells accessed in selecting one word line as a conventional equivalent does.
Specifically, when plate electrode wires are provided along the word lines, one plate electrode wire is selected (or activated) each time a word line is selected. As a result, all the memory cells connected to the selected word line are accessed at the same time. Consequently, the average frequency of access and drawn current in reading or rewriting the data are basically the same as those of a conventional ferroelectric memory. This causes a problem: the number of rewrites increases and it is difficult to reduce power consumption. Particularly in a series-connected TC parallel-unit type ferroelectric RAM, all the driving circuits for the plate electrode wires along the word lines and all the sense amplifiers have to be driven, which makes the power consumption large.
An object of the present invention is to provide a semiconductor memory device capable of reducing the number of accessed memory cells and the power consumption.
Another object of the present invention is to provide a semiconductor memory device capable of preventing an half-selected cell from being read from and read disturb from taking place.
The foregoing objects are accomplished by a semiconductor memory device comprising: a plurality of memory cell blocks each of which comprise a series connection of a plurality of memory cells, each cell being such that both electrodes of a ferroelectric capacitor are connected between the source and drain of each cell transistor; a plurality of bit lines each of which is connected to one end of the plurality of memory cell blocks; and a plurality of plate electrode wires each of which is provided in parallel with the plurality of bit lines and connected to the other end of the plurality of memory cell blocks, with the memory cell blocks connected to the same one of the plurality of bit lines being connected to the same one of the plurality of plate electrode wires.
The foregoing object is further accomplished by a semiconductor memory device comprising: a plurality of memory cells having a plurality of cell transistors and a plurality of ferroelectric capacitors each of which is connected between the source and drain of each of the plurality of cell transistors; a plurality of memory cell blocks each of which comprise a series connection of a specific number of those of the plurality of memory cells; a plurality of bit lines each of which is connected via a select transistor to one end of the plurality of memory cell blocks; a plurality of plate electrode wires each of which is provided in parallel with the plurality of bit lines and connected to the other end of the plurality of memory cell blocks; and a plurality of memory block groups each of which comprise a specific number of those of the plurality of memory cell blocks connected to the same plate electrode wire and the same bit line.
Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out hereinafter.